A computer using a very small and relatively simple instruction set, which allows faster processing and greater compatibility in design between computers.
For the acronym RISC in biology, see RNA-induced silencing complex.The reduced instruction set computer, or RISC, is a CPU design philosophy that favors a simpler set of instructions that all take about the same amount of time to execute.
The idea was originally inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses.
Pre-RISC design philosophy
In the early days of the computer industry, compiler technology did not exist at all. The attitude at the time was that hardware design was easier than compiler design, so the complexity
went into the hardware.
Another force that encouraged complexity was the lack of large memory. When every byte of memory was precious, for example one's entire system only had a few kilobytes of storage, it moved the industry to such features as highly encoded instructions, instructions which could be variable sized, instructions which did multiple operations and instructions which did both data movement and data calculation.
Memory was not only small, but rather slow since they were implemented using magnetic technology at the time.
CPUs had few registers for two reasons:
bits in internal CPU registers are always more expensive than bits in external memory.For the above reasons, CPU designers tried to make instructions that would do as much work as possible. This processor design philosophy eventually became known as Complex Instruction Set Computer (CISC) once the RISC philosophy came onto the scene.
The general goal at the time was to provide every possible addressing mode for every instruction, a principle known as "orthogonality." This led to some complexity on the CPU, but in theory each possible command could be tuned individually, making the design faster than if the programmer used simpler commands.
The ultimate expression of this sort of design can be seen at two ends of the power spectrum, the 6502 at one end, and the VAX at the other. The $25 single-chip 1 MHz 6502 had only a single general-purpose register, but its simplistic single-cycle memory interface allowed byte-wide operations to perform almost on par with significantly higher clocked designs, such as a 4 MHz Zilog Z80 using equally slow memory chips (i.e. The VAX was a minicomputer whose initial implementation required 3 racks of equipment for a single cpu, and was notable for the amazing variety of memory access styles it supported, and the fact that every one of them was available for every instruction.
RISC design philosophy
In the late 1970s researchers at IBM (and similar projects elsewhere) demonstrated that the majority of these "orthogonal" addressing modes were ignored by most programs.
Another discovery was that since these operations were rarely used, in fact they tended to be slower than a number of smaller operations doing the same thing. This seeming paradox was a side effect of the time spent designing the CPUs, designers simply did not have time to tune every possible instruction, and instead tuned only the most used ones.
At about the same time CPUs started to run even faster than the memory they talked to. Even in the late 1970s it was apparent that this disparity was going to continue to grow for at least the next decade, by which time the CPU would be tens to hundreds of times faster than the memory. These additional registers and cache memories would require sizeable chip or board areas that could be made available if the complexity of the CPU was reduced.
Yet another part of RISC design came from practical measurements on real-world programs. For instance, he showed that 98% of all the constants in a program would fit in 13 bits, yet almost every CPU design dedicated some multiple of 8 bits to storing them, typically 8, 16 or 32, one entire word.
Since real-world programs spent most of their time executing very simple operations, some researchers decided to focus on making those common operations as simple and as fast as possible. Since the clock rate of the CPU is limited by the time it takes to execute the slowest instruction, speeding up that instruction -- perhaps by reducing the number of addressing modes it supports -- also speeds up the execution of every other instruction. The focus on "reduced instructions" led to the resulting machine being called a "reduced instruction set computer" (RISC).
Unfortunately, the term "reduced instruction set computer" is often misunderstood as meaning that there are fewer instructions in the instruction set of the processor. Instead, RISC designs often have huge command sets of their own. Inspired by the desire for simpler designs, some people have developed some interesting MISC and OISC machines such as Transport Triggered Architectures, while others have walked into a Turing tarpit.
The real difference between RISC and CISC is the philosophy of doing everything in registers and loading and saving the data to and from them.
Over time the older design technique became known as Complex Instruction Set Computer, or CISC, although this was largely to give them a different name for comparison purposes.
Code was implemented as a series of these simple instructions, instead of a single complex instruction that had the same result.
However RISC also had its drawbacks. At the time it was not clear whether or not there would be a net gain in performance due to this limitation, and there was an almost continual battle in the press and design world about the RISC concepts.
While the RISC philosophy was coming into its own, new ideas about how to dramatically increase performance of the CPUs were starting to develop.
In the early 1980s it was thought that existing design was reaching theoretical limits. A considerable amount of effort was put into designing chips for parallel computing, with built-in communications links.
One idea was to include a pipeline which would break down instructions into steps, and work on one step of several different instructions at the same time. Instead of working on one instruction to add two numbers, these superscalar processors would look at the next instruction in the pipeline and attempt to run it at the same time in an identical unit.
Both of these techniques relied on increasing speed by adding complexity to the basic layout of the CPU, as opposed to the instructions running on them. RISC was tailor-made to take advantage of these techniques, because the core logic of a RISC CPU was considerably simpler than in CISC designs. Although the first RISC designs had marginal performance, they were able to quickly add these new design features and by the late 1980s they were significantly outperforming their CISC counterparts. In time this would be addressed as process improved to the point where all of this could be added to a CISC design and still fit on a single chip, but this took most of the late-80s and early 90s.
The long and short of it is that for any given level of general performance, a RISC chip will typically have many fewer transistors dedicated to the core logic. This allows the designers considerable flexibility; offer the chip for battery-constrained or size-limited applications
Features which are generally found in RISC designs are:
uniform instruction encoding (for example the op-code is always in the same bit position in each instruction, which is always one word long), which allows faster decoding; a homogeneous register set, allowing any register to be used in any context and simplifying compiler design (although there are almost always separate integer and floating point register files);RISC designs are also more likely to feature a Harvard memory model, where the instruction stream and the data stream are conceptually separated; this means that modifying the addresses where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data cache), at least until a special synchronization instruction is issued.
Many of these early RISC designs also shared a not-so-nice feature, the branch delay slot. This instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC, more recent versions of SPARC, and MIPS).
Early RISC
The first system that would today be known as RISC was not at the time; Thornton and Cray designed it as a number-crunching CPU (with 74 op-codes, compared with a 8086's 400) plus 12 simple computers called "peripheral processors" to handle I/O (most of the operating system was in one of these).
Another early load-store machine was the Data General Nova minicomputer, designed in 1968.
The most public RISC designs, however, were the results of university research programs run with funding from the DARPA VLSI Program. The VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics.
UC Berkeley's RISC project started in 1980 under the direction of David Patterson, based on gaining performance through the use of pipelining and an aggressive use of registers known as register windows. In a normal CPU one has a small number of registers, and a program can use any register at any time.
The RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era) RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. Although pipelining was already in use in other designs, several features of the MIPS chip made its pipeline far faster.
The earliest attempt to make a chip-based RISC CPU was a project at IBM which started in 1975, predating both of the projects above. As the name implies, this CPU was designed for "mini" tasks, and when IBM released the IBM RT-PC based on the design in 1986, the performance was not acceptable.
In the early years, the RISC efforts were well known, but largely confined to the university labs that had created them. In fact, almost all modern RISC processors are direct copies of the RISC-II design.
Later RISC
Berkeley's research was not directly commercialized, but the RISC-II design was used by Sun Microsystems to develop the SPARC, by Pyramid Technology to develop their line of mid-range multi-processor machines, and by almost every other company a few years later. It was Sun's use of a RISC chip in their new machines that demonstrated that RISC's benefits were real, and their machines quickly outpaced the competition and essentially took over the entire workstation market.
John Hennessy left Stanford (temporarily) to commercialize the MIPS design, starting the company known as MIPS Computer Systems. Their first design was a second-generation MIPS chip known as the R2000. MIPS designs went on to become one of the most used RISC chips when they were included in the PlayStation and Nintendo 64 game consoles.
IBM learned from the RT-PC failure and went on to design the RS/6000 based on their new POWER architecture. POWER would also find itself moving "down" in scale to produce the PowerPC design, which eliminated many of the "IBM only" instructions and created a single-chip implementation. Companies with existing CISC designs also quickly joined the revolution. Motorola built a new design called the 88000 in homage to their famed CISC 68000, but it saw almost no use and they eventually abandoned it and joined IBM to produce the PowerPC. AMD released their 29000 which would go on to become the most popular RISC design of the early 1990s.
Today the vast majority of all CPUs in use are RISC CPUs, and microcontrollers. RISC design techniques offers power in even small sizes, and thus has come to completely dominate the market for low-power embedded CPUs, which are by far the largest market for processors: while a family may own one or two PCs, their car(s), cell phones, and other devices may contain a total of dozens of embedded processors.
However, despite many successes, RISC has made few inroads into the desktop PC and commodity server markets, where Intel's x86 platform remains the dominant processor architecture (Intel is facing increased competition from AMD, but even AMD's processors implement the x86 platform, or a 64-bit superset known as x86-64). The second is that, although RISC was indeed able to scale up in performance quite quickly and cheaply, Intel took advantage of its large market by spending vast amounts of money on processor development. Intel could spend many times as much as any RISC manufacturer on improving design and manufacturing, making up for flaws inherent in the basic x86 architecture, the same could not be said about smaller firms like Cyrix and NextGen but they all realized that they could apply RISC design philosophies and practices to Intel's architecture. The first x86 CPU to deploy RISC techniques was the NextGen Nx586, released in 1994, and it did this by expanding the majority of the CISC instructions into multiple simpler RISC operations.
Consumers are interested in speed, cost per chip, and compatibility with existing software rather than the cost of development of new chips. As the complexity of developing ever more advanced CPUs rises, the cost of both development and fabrication of high-end CPUs has exploded. The cost gains given by RISC are now dwarfed by the high costs of developing any modern CPU. The result is that virtually all RISC platforms with the exception of IBM's Power Architecture have greatly shrunk in scale of development of high performing CPUs (like SPARC and MIPS) or were abandoned (like Alpha and PA-RISC) during the 00s. As of 2004, x86 chips are the fastest CPUs in SPECint displacing all RISC CPUs, and the fastest CPU in SPECfp is the IBM Power 5 processor.
Still, RISC designs have led to a number of successful platforms and architectures, some of the larger ones being:
MIPS's MIPS line, found in most SGI computers and the PlayStation, PlayStation 2, PlayStation Portable, and Nintendo 64 game consoles IBM's and Freescale's (formerly Motorola SPS) Power Architecture, used in all of IBM's supercomputers, midrange servers and workstations, in Apple's Power Macintosh computers, in Nintendo's Gamecube and Wii, Microsoft's Xbox 360 and Sony's PlayStation 3 game consoles, and in many embedded applications like printers and cars. originally used the (CISC) Motorola 680x0 processors in its early PDAs, but now uses (RISC) ARM processors in its latest PDAs. Also, many cell phones from, for example, Nokia are based on ARM designs.Alternative term
Over many years, RISC instruction sets have tended to grow in size. Thus, some have started using the term "load-store" to describe RISC processors, since this is the key element of all such designs.
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